The present invention is directed generally to digital apparatus, and more particularly to a technique for distributing a master clock signal on an integrated circuit chip to minimize clock skew.
Today's microelectronic industry has seen amazing advances in the art of fabricating semiconductor integrated circuits, achieving extremely high device counts for individual integrated circuit chips. However, notwithstanding the very large scale integration capable today, both integrated circuit chips are fabricated with the knowledge that they will be incorporated into yet a larger design. Thus, for example, computing systems are often formed by utilizing even very large scale integrated (VLSI) circuit chips mounted to circuit boards, and interconnected to one another.
More often than not such systems are synchronous in the sense that they include clocked devices (e.g., flip flops or other bi-stable elements) whose state changes will occur, in response to an edge of a clock signal. In such synchronous systems it is often desirable that the individual (integrated circuit) devices or modules provide informational signals (e.g., data, control signals, etc.) or receive such informational control signals synchronously; that is, that the signals be present, or presented, in a steady state condition relative to an edge of the clock signal.
This is sometimes not an altogether easy task, particularly for high frequency operation (e.g., in the mega-hertz range) due to chip skew i.e., difference between a transition of a clock signal applied to a device or chip and a state change of an output signal as a result of the clock transition. For example, a large number of internal (to the device) clock loads (flip-flops) can cause a corresponding large on-chip skew and a chip-to-chip skew due to delay differences at individual clock loads. (Chip-to-chip skew is mainly due to semiconductor process variations and the number of clock loads on different chips, assuming the temperature and supply voltage variations at the system level are negligible.) In order to ensure a proper exchange of data signals between individual devices, on-chip as well as chip-to-chip skew must be controlled.
One solution is to form a phase lock loop (PLL) on each integrated circuit chip. The PLL can be structured to operate to receive the clock signal to produce therefrom a number of synchronous (phase related) clock signals, maintaining a strict phase relationship between the clock signals it produces and the received clock by the chip. Other techniques may require the PLL of one chip to receive the clock signals of other chips with which it will operate in order to maintain a proper phase relationship between the clock it utilizes and the clocks that the other chips utilize.
Depending upon the particular scheme implemented, the use of PLL devices is not without certain problems. Use of a PLL often requires the addition of extra pins to the chip, as well as the addition of extra discrete components (resistors, and capacitors for the loop filter). Also, dedicated (noise free) analog power supply and ground may be needed in the design.
Another approach is to pass data from one clock regime to another clock regime through an intermediate clock regime. This also requires additional circuitry to implement the intermediate clock regime.